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Compact mode
Last change: 14.06.2011 15:01
Profile views: 864
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Code name:
SSE
Architecture:
ЦПУ CPU - Ядер Z TXT Report - Потоков
Revision:
2-way set associative
Technology:
64-byte line size L1 Instruction cache 2 x 64 KBytes μ
Family / Model / Stepping:
SSE3 - Расшир. SSE4A
Instructions:
2-way set associative
Socket:
device 24
Core frequency:
64-byte line size L2 cache 2 x 512 KBytes МГц
Bus speed:
64-byte line size FID/VID Control yes FID range 4.0x - 11.5x Max VID 1.175 V P-State FID 0x7 - VID 0x1E - IDD 10 (11.50x - 1.175 V) P-State FID 0x5 - VID 0x22 - IDD 9 (10.50x - 1.125 V) P-State FID 0x10E - VID 0x2D - IDD 6 (7.50x - 0.987 V) P-State FID 0x106 - VID 0x35 - IDD 4 (5.50x - 0.887 V) P-State FID 0x100 - VID 0x40 - IDD 2 (4.00x - 0.750 V) Package Type 0x2 Model 21 String 1 0x1 String 2 0xF Page 0x0 CmpCap 2 ApicIdCoreSize 4 TDC Limit 20 Amps Attached device PCI device at bus 0 МГц
Multiplier:
x 16-way set associative
QPI:
function 3 Attached device PCI device at bus 0 МГц
Level 1 cache:
Данные: function 1 Attached device PCI device at bus 0 КБайт / Инструкции: device 24 КБайт
Level 2 cache:
device 24 КБайт
Level 3 cache:
function 2 Attached device PCI device at bus 0 КБайт
CPU-Z version:
device 0 (0x0)
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