Code name
SSE
Architecture
ЦПУ CPU - Ядер Z TXT Report - Потоков
Revision
2-way set associative
Technology
64-byte line size L1 Instruction cache 4 x 64 KBytes μ
Family / Model / Stepping
SSE3 - Расшир. SSE4A
Instructions
2-way set associative
Socket
device 24
Core frequency
64-byte line size L2 cache 4 x 512 KBytes МГц
Bus speed
64-byte line size FID/VID Control yes FID range 4.0x - 15.0x Max VID 1.375 V # of P-States 4 P-State FID 0xE - VID 0x0E - IDD 19 (15.00x - 1.375 V) P-State FID 0x7 - VID 0x16 - IDD 14 (11.50x - 1.275 V) P-State FID 0x2 - VID 0x1E - IDD 13 (9.00x - 1.175 V) P-State FID 0x100 - VID 0x2A - IDD 8 (4.00x - 1.025 V) Package Type 0x1 Model 40 String 1 0xA String 2 0x6 Page 0x0 CmpCap 4 ApicIdCoreSize 4 TDC Limit 76 Amps Boosted P-States 0 Max non-turbo ratio 15.00x Max turbo ratio 15.00x Max CPU COF 30 Core Performance Boost no P-State 0 МГц
Multiplier
x 16-way set associative
QPI
function 1 Attached device PCI device at bus 0 МГц
Level 1 cache
Данные: FID 0x100 - VID 0x2A (4.00x - 1.025 V) Attached device PCI device at bus 0 КБайт / Инструкции: FID 0x2 - VID 0x1E (9.00x - 1.175 V) P-State 3 КБайт
Level 2 cache
device 24 КБайт
Level 3 cache
function 0 Attached device PCI device at bus 0 КБайт
CPU-Z version
device 0 (0x0)